1. Field of the Invention
The present invention relates to a non-volatile semiconductor memory device and a fabricating method thereof, and more particularly to a non-volatile semiconductor memory device and a fabricating method thereof, which prevents mismatching between a split floating gate and a control gate, so that there will be no different characteristics of memory cells in response to odd/ even numbered word line.
2. Description of the Prior Art
In general, a non-volatile semiconductor memory device has recently shown a tendency to be widely used in a variety of fields since it can not only erase/store data with electrical connection, but also store data without supply of electricity. These memory cells of the non-volatile semiconductor memory device are classified into NAND type and NOR type.
There are different advantages in those NAND and NOR types of memory cells in response to the trend of becoming high integration and high speed of memory cells, so that they have been increasingly used in a variety of applications to make the best use of those advantages of respective types.
The NOR type of the non-volatile semiconductor memory device comprises a plurality of memory cells having a transistor at a bit line connected in parallel and only one memory cell transistor positioned between a drain connected to the bit line and a source connected to a common source line. There is an advantage in the NOR type of a non-volatile semiconductor memory device in that the current of memory cells is high enough to operate at high speed, but a disadvantage in that it is difficult to have a high integration due to large area taken by the contact of bit lines and source lines.
The NOR type of the non-volatile memory device is constructed in a deposition structure in which a floating gate and a control gate are deposited with an insulation interlayer therebetween, and the processes thereof will be described below.
First of all, in programming data, when voltage is applied to the bit line and the control gate connected with the drain of memory cells, electric current flows between the source and the drain, so that electrons are injected into the floating gate by a channel hot electron injection mechanism. As a result, data are programmed.
In erasing, when voltage is applied to a source, electrons are flown out of the floating gate by a Fowler-Nordheim tunneling mechanism. As a result, data are erased.
In reading, when adequate voltage is applied to the bit line and the control gate of the selected memory cells, the presence of current at the selected memory cell transistor is read. As a result, data are read.
As memory cells are connected in parallel to the bit line in the non-volatile memory device, if the threshold voltage of the memory cell transistor gets lower than the voltage (usually 0V) applied to the control gate of the not-selected memory cells, current flows between the source and the drain, regardless of the ON/OFF state of the selected memory cells, an operational failure (wrong operation) occurs that all the memory cells may be read as the ON state thereof. Thus, there is a difficulty in the nonvolatile memory device that the threshold voltage should be strictly controlled. Also, because excessive amount of current flows at the memory cells in programming data by the channel hot electron injection mechanism, a high capacity of the pump may be required for generating the voltage in programming data.
In order to solve the aforementioned problem, the non-volatile semiconductor memory devices in a variety of structures, commonly called a split gate type, have been suggested. A representative example of all has been disclosed in U.S. Pat. No. 5,045,488 titled as a xe2x80x9cMETHOD OF MANUFACTURING A SINGLE TRANSISTOR NON-VOLATILE, ELECTRICALLY ALTERABLE SEMICONDUCTOR MEMORY DEVICE.xe2x80x9d
As shown in FIGS. 1 through 3, the non-volatile semiconductor memory device disclosed therein comprises: an active area 11 of a substrate 10 isolated by a field insulating layer 13; a pair of floating gates 15 arranged at a first gate insulating layer of the active area 11 with a source area 17 therebetween; an oxide layer 19 positioned at the floating gates 15; second gate insulating layers 21 positioned at the lateral surfaces of the floating gates 15 to be used for tunneling in erasing data; and control gates 23 simultaneously overlapping an external side of the floating gates 15, the second gate insulating layer 21 and a part of the drain area 18, that is, extensively from an external portion of the floating gate 15 to a part of the drain area 18. An interlayer 25 is deposited at the aforementioned structure, and a bit line 27 is formed for electrical connection through a contact hole 26 to the drain area 18.
At this time, the channel areas formed by the floating gates 15 and the control gates 23 are connected in series. The area marked with a dot line represents a unit cell area (UCA). L1 and L2 respectively symbolize gate lengths of selected memory cell transistors. Even if only a pair of floating gates corresponding to an active area 110 are shown in the drawings for convenient description, it should be taken for granted that a number of pairs of floating gates are repeatedly arranged correspondingly to the active areas 110 in actuality.
Operation of the conventional non-volatile semiconductor memory device thus constructed will be described below. First of all, in programming data, if a high voltage is applied to the source area 17 of the UCA, the floating gate 15 is induced into a predetermined voltage by a coupling phenomenon. Then, if a voltage, for example, higher than the threshold voltage of the transistor formed by the control gate and the channel formed by the floating gate 15 is applied to the control gate 23, current flows between the source area 17 and the drain area 18. At this time, the channel hot electron injection mechanism is performed, so that electrons are injected into the floating gate 15. As a result, data is programmed.
Therefore, if voltage applied to the control gate 23 is properly controlled, hot electrons can be formed at a lower end of the floating gate 15 and the electric field gets strong enough to improve the data programming efficiency. In addition, the current flowing between the source area 17 and the drain area 18 can also be restricted to reduce power consumption, thereby no longer requiring a high capacity of a pump to be used at the stacked NOR type of the non-volatile memory device.
In erasing data, if a high voltage is applied to the control gate 23, the electrons collected at the floating gate 15 are flown out through the second gate insulating layer 21 by the electric field formed between the control gate 23 and the floating gate 15. As a result, data are erased.
In reading data, if a predetermined voltage is applied to the bit line 27 and the control gate 23 connected with the drain area 18 of the memory cells, data can be read in accordance with the presence of the current flowing between the memory cells. At this time, if the channel area formed by the control gate 23 and the channel formed by the floating gate 15 are all made, that is, if voltage, higher than the threshold voltage, is applied to the gate, the non-volatile memory cells flow current.
In general, the select transistors of the memory cells are manufactured to have threshold voltage (Vth) of approximately 1.0V. The floating gate 15 has a high threshold voltage at the data programmed memory cells and a low threshold voltage at the data erased memory cells including xe2x88x92Vth sometimes. However, in case that the floating gate 15 has xe2x88x92Vth due to over-erasure, the select transistor having a threshold voltage of approximately 1.0V turns off the channel even if 0V is applied to the control gate 23. Therefore, there will be not problem of over-erasure any longer. In this way, even if the threshold voltage of the floating gate of the NOR type of the non-volatile semiconductor device is not strictly controlled, an operational failure (wrong operation) will not occur.
However, the floating gate pattern and the control gate pattern are simultaneously formed in a general self-aligned deposition gate type of memory cells, so that misalignment of these two patterns will not easily happen.
On the other hand, since the floating gate pattern and the control gate patterns of a conventional split gate type of memory cells are fabricated by separate processes, misalignment of these two patterns may easily happen in forming the control gate pattern. Without mismatching, the length of the select transistor gates, L1 and L2 will be the same. With mismatching, the length of the select transistor gates L1 and L2 will be different, so that there will be a tendency of showing different characteristics of memory cells in accordance with odd/even numbered word lines.
Besides, byte programming and erasing processes can not be performed due to a schematic characteristic of the memory cells. Furthermore, since one contact hole is used in each bit line, the number of contact holes of bit lines is large, which has been a factor to cause difficulty in scaling down cells.
Therefore, it is an object of the present invention to prevent mismatching of word lines, thereby not showing different characteristics of memory cells in response to with odd/even numbered word lines.
It is another object of the present invention to make it possible to perform byte programming and erasing processes.
It is a third object of the present invention to reduce the number of contact holes used at bit lines, thereby easily scaling down cells.
In order to accomplish the aforementioned objects of the present invention, there is provided a non-volatile semiconductor memory device comprising:
a first conductivity type of a semiconductor substrate having separately formed active areas and field areas formed with field insulating layers to isolate the active areas;
a first gate insulating layer formed at respective substrate of the active areas;
floating gates arranged at a predetermined interval on the first gate insulating layer;
oxide layers respectively formed at the upper surface of the floating gates;
a second gate insulating layer to be used as a tunneling insulating layer formed at lateral surfaces of the floating gates;
control gates respectively formed at the active areas of the resultant structure for getting a corresponding pair of floating gates, out of the floating gates, continuously overlapped;
a second conductivity type of source areas formed at the active area, a part of which is overlapped with the same part of the floating gates, and at a part of the neighboring active area; and
a second conductivity type of buried diffusion areas formed at the substrate of a part of the field area for preventing neighboring source areas of the same source line, out of source areas, from being isolated by the field insulating layer, and for making them electrically connected.
Preferably, the buried diffusion area is formed at the substrate of the periphery of the field insulating layer formed between neighboring source areas. The field insulating layer is an insulating layer filled in the trench.
In addition, a non-volatile semiconductor memory device in accordance with another embodiment of the present invention comprises:
a first conductivity type of a semiconductor substrate having separately formed first active areas, active areas formed between the first active areas with second active areas integrally connected to parts of both sides of the first active areas and field areas formed with a field insulating layer for isolating the active areas;
first gate insulating layers respectively formed at the substrate of the first and second active areas;
floating gates arranged at the first gate insulating layer in a predetermined interval;
oxide layers respectively formed at the upper surfaces of the floating gates;
second gate insulating layers, to be used as tunneling insulating layers, formed at the lateral surfaces of the floating gates;
control gates formed at the first active areas of the resultant structure for getting a corresponding pair of floating gates, out of the floating gates, continuously overlapped; and
a second conductive type of active source areas formed at the first active areas, a part of which is overlapped at the same portion of the floating gates, and at a part of the neighboring first active areas, wherein the second active areas are integrally connected between the source areas to prevent the neighboring source areas of the same source line, out of the source areas, from being isolated by the field insulating layer and to make them electrically connected.
Preferably, the second active areas are ion-implanted with a second conductive type of impurity.
The method of fabricating the non-volatile semiconductor memory device in accordance with the first embodiment of the present invention comprises the steps of:
forming a field insulating layer at a field area of the semiconductor substrate for isolating active areas of the first conductivity type of a semiconductor substrate;
forming first gate insulating layers at the active areas of the substrate;
respectively forming floating gates arranged at the first gate insulating layers in a predetermined interval and oxide layers at the upper surfaces of the floating gates;
forming a second conductivity type of source areas at the substrate of the active areas for getting a part thereof partially overlapped with the same part of the floating gates;
forming second gate insulating layers, to be used for tunneling insulating layers, at the lateral surfaces of the floating gates; and
forming control gates at the active areas of the resultant structure for getting a corresponding pair of the floating gates, out of the floating gates, continuously overlapped,
wherein the step of forming the field insulating layer includes the step of forming a second conductivity type of buried diffusion areas at the substrate of a part of the field areas positioned between neighboring source areas for preventing the source areas neighboring the same source line, out of all the source areas, from being isolated by the field insulating layer, and for making them electrically connected.
A method of fabricating the non-volatile semiconductor memory device in accordance with another embodiment of the present invention comprises the steps of:
forming a first active areas of a first conductivity type of semiconductor substrate and field insulating layers at the field areas of the semiconductor substrate for isolating active areas positioned between the first active areas with the second active areas integrally connected to a part of both sides of the first active areas;
respectively forming a first gate insulating layer at the substrate of the first and second active areas;
forming floating gates arranged in a predetermined interval at the first gate insulating layer and oxide layers at the upper surfaces of the floating gates;
forming a second conductivity type of source areas at the substrate of the active areas for getting a part thereof overlapped with the same parts of the floating gates;
forming a second gate insulating layer, to be used for tunneling insulating layers, at the lateral surfaces of the floating gates; and
forming control gates on the first active areas of the resultant structure for getting a corresponding pair of the floating gates, out of the floating gates, continuously overlapped,
wherein the second active areas are integrally connected between neighboring source areas for preventing the source areas neighboring the same source line, out of all the source areas, from being isolated by the field insulating layers, and for making them electrically connected.
Therefore, in accordance with the present invention, the control gates continuously overlap a pair of split floating gates of the active areas. As a result, even if the floating gate pattern and the control gate pattern are respectively made by separate processes, there will be no mismatching between the aforementioned two patterns. There will be no tendency of showing different characteristics of memory cells in accordance with odd/even numbered word lines.
In addition, the schematic characteristic of cells makes it possible to program and erase a byte. As one contact hole is not used at each bit line, the number of contact holes gets small, thereby making it possible to scale down cells.